In traditional, an operational amplifier generally includes a differential amplification circuit as a differential input stage for amplifying and outputting an input signal and a source-grounded circuit as an output stage for providing a load driving function and amplifying the signal. As a differential amplification circuit, there are a first configuration in which an output voltage can be taken out in a range smaller than a high potential side power supply voltage and a low potential side power supply voltage by about one to two V and a second configuration in which the output voltage can be taken out in a range substantially equal to a voltage range between the high potential side power supply voltage and the low potential side power supply voltage.
In general, the first configuration includes one of a P-channel MOS transistor (referred to as PMOS below) and an N-channel MOS transistor (referred to as NMOS below), and the second configuration includes both the PMOS and the NMOS (for example, differential pair of PMOSs and differential pair of NMOSs). Furthermore, a differential output type is advantageous to common noise resistance and low distortion of an output waveform. Therefore, when ranges of power supply are the same, a range of an acceptable common level of the second configuration becomes wider than that of the first configuration. Conversely, when the ranges of the acceptable common levels are the same, the second configuration can lower the power supply voltage of the operational amplifier than the first configuration.
FIG. 9 is a diagram of an exemplary operational amplifier according to the second configuration, and a differential output type second configuration is exemplified.
An operational amplifier 1 has three operation regions according to input ranges of input voltages Vin and xVin. A first one is a first operation region on a side of a low potential side power supply Vss in which an NMOS differential pair 2 is turned off and a PMOS differential pair 3 operates since a DC level (common level) is too low. A second one is a second operation region on a side of a high potential side power supply Vdd in which the PMOS differential pair 3 is turned off and the NMOS differential pair 2 operates since the DC level (common level) is too high. A third one is a third operation region in which both the NMOS differential pair 2 and the PMOS differential pair 3 operate.
As the first operation region and the second operation region, in a case of the input range in which one of the PMOS differential pair 3 and the NMOS differential pair 2 included in the differential amplification circuit is turned off, a load transistor operates in a non-saturation region. Therefore, there is a problem in that a transconductance is significantly decreased and a gain of the operational amplifier is reduced.
For example, in a case of the first operation region, a current for flowing in the NMOS differential pair 2 becomes zero, and a value of a current for flowing in load transistors 4p and 5p becomes I which is half of a traditional value. At this time, a bias Pbias1 of the load transistors 4p and 5p is a voltage value for causing a current having a current value 2I to flow. Therefore, drain voltages of the load transistors 4p and 5p are increased, and the load transistors 4p and 5p operate in the non-saturation region. By following this, operations of load transistors 6p and 7p are changed to operations in the non-saturation region. Since a Gm is small in the non-saturation region, the gain of the amplifier is reduced.
Also, for example, in a case of the second operation region, a current for flowing in the PMOS differential pair 3 becomes zero, and a value of a current for flowing in load transistors 4n and 5n becomes I which is half of a traditional value. At this time, a bias Nbias1 of the load transistors 4n and 5n is a voltage value for causing a current having a current value 2I to flow. Therefore, drain voltages of the load transistors 4n and 5n are increased, and the load transistors 4n and 5n operate in the non-saturation region.
By following this, operations of the load transistors 6n and 7n are changed to operations in the non-saturation region. Since a Gm is small in the non-saturation region, the gain of the amplifier is reduced.
As a technology coping with this problem, for example, there is a single-ended output configuration. This configuration can relax the reduction in the gain.
Also, for example, as illustrated in FIG. 10, a system can be considered which detects an input level by arranging a level detector at an input end of the operational amplifier and compensates a DC current, which should be originally flowed, in an input stage which is turned off. With this system, the load transistor can continue to operate in the saturation region.
Also, for example, Patent Document 1 indicates a configuration in which a current compensation mirror circuit as a feedback path for detecting an input level of an operational amplifier and adding a current has been provided.